Intel Xe-HPC Ponte Vecchio: Over 100 billion transistors and 47 tiles (update)

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As part of yesterday’s presentation of the realignment in manufacturing, Intel also announced further details on the Xe HPC chip Ponte Vecchio. At the beginning of January, Intel announced that the first chips had returned from production and were being tested in the laboratories. The packaging of Ponte Vecchio (Foveros and EMIB) plays a central role for Intel’s future GPUs and processors – not only for Ponte Vecchio.

Intel confirmed yesterday that a Xe HPC chip consists of 47 tiles (that’s what Intel calls its chiplets). A few weeks ago, Raja Koduri named 41 chiplets / tiles. How this discrepancy is to be understood and whether Koduri only meant the active components, while Intel listed all chip sets (including the passive ones) yesterday, is not known. In addition, Intel confirmed that all tiles together have over 100 billion transistors. For comparison: NVIDIA’s GA100 GPU, which is manufactured in 7 nm, has 54 billion transistors and an area of ​​826 mm² – but it also has a monolithic design.

A video (see embedded tweet at the end of this message) also shows how several Xe-HPC chips “roll off the assembly line” in a production line. The huge package can also be seen several times.

Finally, Intel grants an interesting look into the laboratory in Folsom. Here you can see Xe-HPC Ponte Vecchio in action. The development hardware is water-cooled. The development board on which the chip sits also has two EPS connections. According to the command line, the Xe-HPC cards were operated on systems with Sapphire Rapids (SPR), i.e. the next but one Xeon generation. Sapphire Rapids will consist of up to four chiplets, support PCI-Express 5.0 (based on its Compute Express Link) and DDR5.

Intel Xe-HPC Ponte Vecchio




Intel plans to work with the US Department of Energy (DOE) near Chicago to build the first ExaFLOPS system in the USA. The system is to be operated by the Argonne National Laboratory. The special thing about the Aurora supercomputer: All important components should come from Intel. This applies particularly to the processors (Xeon Scalable of the 4th generation, Sapphire Rapids) and the GPU accelerators (Ponte Vecchio, Xe-HPC). Intel’s Optane DC Persistent Memory should also be used.

The supercomputer was originally supposed to be built in 2021. However, due to the problems in production and the general situation, this deadline is unlikely to be kept.

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Update: Intel clears up

When we asked Raja Koduri, Senior Vice President of the new graphics division “Core and Visual Computing” at Intel, answered the question about the number of tiles. Accordingly, when specifying the 41 tiles from January, the HBM chips were not counted.

In addition, Koduri breaks down the individual tiles again with the production:

  • 16x Xe HPC (internal and external production)
  • 8x Rambo (internal production)
  • 2x Xe Base (internal production)
  • 11x EMIB (internal production)
  • 2x Xe Link (external production)
  • 8x HBM (external production)

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Intel XeHPC Ponte Vecchio billion transistors tiles update

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